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document # sram125 rev f revised november 2008 three-state outputs fully ttl compatible inputs and outputs advanced cmos technology automatic power down packages 32-pin 600 mil plastic and ceramic dip 32-pin 445 mil sop 32-pin tsop 32-pin lcc (400x820 mil) [two-sided] p4c1024l low power 128k x 8 cmos static ram locations are specifed on address pins a 0 to a 16 . reading is accomplished by device selection ( ce 1 low and ce 2 high) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce 1 or oe is high or we or ce 2 is low. the p4c1024l is packaged in a 32-pin tsop, 445 mil sop, 600 mil pdip, or 32-pin lcc package. the p4c1024l is a 1,048,576-bit low power cmos static ram organized as 128kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times of 55 ns and 70 ns are availale. cmos is utilized to reduce power consumption to a low level. the p4c1024l device provides asynchronous op - eration with matching access and cycle times. memory v cc current (commercial/industrial) operating: 70ma/85ma cmos standby: 100a/100a access times 55/70 (commercial or industrial) single 5 volts 10% power supply easy memory expansion using ce 1, ce 2 and oe inputs common data i/o functional block diagram pin configuration dip (p600, c10), sop (s12), lcc (l1) top view see end of datasheet for tsop pin confguration. description
p4c1024l - low power 128k x 8 cmos static ram page 2 document # sram125 rev f recommended operating temperature & supply voltage maximum ratings (1) stresses greater than those listed can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. exposure to maximum ratings for extended periods can adversely affect device reliability. dc electrical characteristics (over recommended operating temperature & supply voltage) (2) temperature range (ambient) supply voltage commercial (0c to 70c) 4.5v v cc 5.5v industrial (-40c to 85c) military (-55c to +125c) sym parameter min max unit v cc supply voltage with respect to gnd -0.5 7.0 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 v cc + 0.5 v t a operating ambient temperature -55 125 c s tg storage temperature -65 150 c i out output current into low outputs 25 ma i lat latch-up current > 200 ma sym parameter test conditions min max unit v oh output high voltage (i/o 0 - i/o 7 ) i oh = C1ma, v cc = 4.5v 2.4 v v ol output low voltage (i/o 0 - i/o 7 ) i ol = 2.1ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage -0.5 0.8 v i li input leakage current gnd v in v cc mil -10 +10 a ind -5 +5 com -2 +2 i lo output leakage current gnd v out v cc , ce 1 v ih or ce 2 v il mil -10 +10 a ind -5 +5 com -2 +2 i sb v cc current ttl standby current (ttl input levels) v cc = 5.5v, i out = 0 ma ce 1 = v ih or ce 2 = v il 3 ma i sb1 v cc current cmos standby current (cmos input levels) v cc = 5.5v, i out = 0 ma ce 1 v cc -0.2v, ce 2 0.2v 100 a
p4c1024l - low power 128k x 8 cmos static ram page 3 document # sram125 rev f * tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. the device is continuously enabled for writing, i.e., ce 2 v ih (min), ce 1 and we v il (max), oe is high. switching inputs are 0v and 3v. **as above but @ f=1 mhz and v il / v ih = 0v/ v cc . capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0 mhz) power dissipation characteristics vs. speed ac electrical characteristics - read cycle (over recommended operating temperature & supply voltage) symbol parameter test conditions max unit c in input capacitance v in =0v 7 pf c out output capacitance v out =0v 9 pf symbol parameter temperature range * ** unit -55 -70 -55 -70 i cc dynamic operating current commercial 70 70 15 15 ma industrial/military 85 85 25 25 ma symbol parameter -55 -70 unit min max min max t rc read cycle time 55 70 ns t aa address access time 55 70 ns t ac chip enable access time 55 70 ns t oh output hold from address change 5 5 ns t lz chip enable to output in low z 10 10 ns t hz chip disable to output in high z 20 25 ns t oe output enable low to data valid 30 35 ns t olz output enable low to low z 5 5 ns t ohz output enable high to high z 20 25 ns t pu chip enable to power up time 0 0 ns t pd chip disable to power down time 55 70 ns
p4c1024l - low power 128k x 8 cmos static ram page 4 document # sram125 rev f notes: 1. we is high for read cycle. 2. ce 1 and oe is low, and ce 2 is high for read cycle. 3. address must be valid prior to, or coincident with later of ce 1 transition low or ce 2 transition high. read cycle no. 1 ( oe controlled) (1) read cycle no. 2 (address controlled) read cycle no. 3 ( ce controlled) 4. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 5. read cycle time is measured from the last valid address to the frst transitioning address.
p4c1024l - low power 128k x 8 cmos static ram page 5 document # sram125 rev f notes: 6. ce 1 and we are low and ce 2 is high for write cycle. 7. oe is low for this write cycle to show twz and tow. 8. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high impedance state. 9. write cycle time is measured from the last valid address to the frst transitioning address. ac characteristics - write cycle (over recommended operating temperature & supply voltage) write cycle no. 1 ( we controlled) (6) symbol parameter -55 -70 unit min max min max t wc write cycle time 55 70 ns t cw chip enable time to end of write 50 60 ns t aw address valid to end of write 50 60 ns t as address set-up time 0 0 ns t wp write pulse width 40 50 ns t ah address hold time 0 0 ns t dw data valid to end of write 25 30 ns t dh data hold time 0 0 ns t wz write enable to output in high z 25 30 ns t ow output active from end of write 5 5 ns
p4c1024l - low power 128k x 8 cmos static ram page 6 document # sram125 rev f timing waveform of write cycle no.2 ( ce controlled) (6) * including scope and test fxture. note: because o the high speed o the p4c1024l care must be taken hen testing this device an inadequate setup can cause a normal unctioning part to be reected as aulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor to avoid signal refections, proper termination must be used; for example, w w w w ac test conditions truth table figure 1. output load figure 2. thevenin equivalent input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reerence level 1.5v output timing reerence level 1.5v output load see fig. 1 and 2 mode ce 1 ce oe we i/o o o w i
p4c1024l - low power 128k x 8 cmos static ram page 7 document # sram125 rev f symbol parameter test conditions min max unit v dr v cc for data retention ce 1 v cc -0.2v, ce 2 0.2v, v in v cc -0.2v or v in 0.2v 2.0 5.5 v i ccdr (1) data retention current v dr = 2.0v 30 a v dr = 3.0v 50 a t cdr chip deselect to data retention time see retention waveform 0 ns t r operating recovery time 5 ms data retention 1. ce 1 t v dr -0.2v, ce 2 t v dr -0.2v or ce 2 d 0.2v; or ce 1 d 0.2v, ce 2 0.2v; v in t v dr -0.2v or v in d 0.2v low v cc data retention waveform 1 ( ce 1 controlled) low v cc data retention waveform 2 (ce 2 controlled) t c d r t r d a t a r e t e n t i o n m o d e v d r c e 2 - 0 . 2 v 2 . 2 v 4 . 5 v v i l 4 . 5 v v c c c e 2 v i l
p4c1024l - low power 128k x 8 cmos static ram page 8 document # sram125 rev f selection guide the p4c1024l is available in the following temperature, speed and package options. ordering information temperature range package speed -55 -70 commercial plastic dip (600 mil) -55pc -70pc plastic sop (445 mil) -55sc -70sc tsop -55tc -70tc ceramic dip (600 mil) -55cwc -70cwc industrial plastic dip (600 mil) -55pi -70pi plastic sop (445 mil) -55si -70si tsop -55tc -70tc ceramic dip (600 mil) -55cwi -70cwi military processed* lcc [two-sided] -55l1mb -70l1mb * military temperature range with mil-std-883, class b compliance
p4c1024l - low power 128k x 8 cmos static ram page 9 document # sram125 rev f tsop pin configuration pkg # l1 # pins 32 symbol min max a 0.080 0.100 b 0.022 0.028 b1 0.006 0.022 b2 0.040 - d 0.800 0.840 e 0.392 0.400 e 0.050 bsc h 0.012 ref l 0.070 0.080 l1 0.090 0.110 l2 0.003 0.015 n 32 rectangular leadless chip carrier [two-sided]
p4c1024l - low power 128k x 8 cmos static ram page 10 document # sram125 rev f pkg # s12 # pins 32 (445 mil) symbol min max a - 0.118 a1 0.004 - a2 0.101 0.111 b 0.014 0.020 c 0.006 0.012 d 0.793 0.817 e 0.050 bsc e 0.440 0.450 h 0.546 0.566 l 0.023 0.039 l1 0.047 0.063 0 4 pkg # p600 # pins 32 (600 mil) symbol min max a 0.160 0.200 a1 0.015 - b 0.014 0.023 b2 0.045 0.070 c 0.006 0.014 d 1.600 1.700 e1 0.526 0.548 e 0.590 0.610 e 0.100 bsc eb 0.600 bsc l 0.120 0.150 0 15 plastic dual in-line package soic/sop small outline ic package
p4c1024l - low power 128k x 8 cmos static ram page 11 document # sram125 rev f tsop thin small outline package (8 x 20 mm) pkg # t3 # pins 32 symbol min max a - 0.048 a 2 0.037 0.042 b 0.006 0.011 d 0.720 0.729 e 0.307 0.323 e 0.50 mm bsc h d 0.779 0.796 sidebrazed dual in-line package pkg # c10 # pins 32 (600 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.680 e 0.510 0.620 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 -
p4c1024l - low power 128k x 8 cmos static ram page 12 document # sram125 rev f revisions document number sram 125 document title p4c1024l low power 128k x 8 cmos static ram rev issue date originator description of change or 1997 jdb new data sheet a oct-2005 jdb changed logo to pyramid b feb-2006 jdb added tsop package c sep-2006 jdb added ceramic dip package d may-2007 jdb corrected errors in p600 package dimensions e nov-2008 jdb added l1 package, lead-free option f nov-2008 jdb changed layout and formatting, no signifcant changes to content

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